Field
Aspects of the present disclosure relate to semiconductor devices, and more particularly to reducing gate length and spacing in field effect transistor (FET) structures.
Background
As semiconductor device sizes decrease, the ability to create the patterns for the devices becomes more difficult. For 10 nanometer (nm) contacted polysilicon (PO) pitch (CPP) devices, multiple patterning steps may be used to attain the device size. For example, a related art method is known as litho-etch (LELE), which uses a larger pitch pattern that is interleaved or intertwined to achieve smaller pitch sizes. Nevertheless, LELE is still limited by a larger line edge roughness (LER), a larger gate-gate space variation, and a larger critical dimension variation.
Another related art method is self-aligned double patterning (SADP) that uses a spacer deposited on a mandrel to define the gate length (Lg). Although SADP has better critical dimension uniformity than LELE, additional masks are used to produce different gate lengths in a SADP-produced device. This limits the usefulness of the SADP process for larger integrated circuits.